HD404369 Datasheet, PDF (81/117 Pages) Hitachi Semiconductor – 4-bit HMCS400-Series microcomputer

Transfer completion
(IFS ← 1)
Interrupts inhibited
IFS ← 0
SMR write
HD404369 Series
Yes
IFS = 1
Transmit clock
error processing
No
Normal
termination
Transmit clock error detection flowchart
State
Transmit clock
wait state
SCK pin (input)
1
SMR write
Transfer state
Transmit clock wait state
Transfer state
Noise
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit clock
error. When SMR is written,
IFS is set.
IFS
Flag set because octal
counter reaches 000
Flag reset at
transfer completion
Transmit clock error detection procedure
Figure 61 Transmit Clock Error Detection
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written by the following registers.
 Serial Mode Register (SMR: $005)
 Serial Data Register (SRL: $006, SRU: $007)
 Port Mode Register A (PMRA: $004)
 Port Mode Register C (PMRC: $025)
 Miscellaneous Register (MIS: $00C)
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