HD404369 Datasheet, PDF (13/117 Pages) Hitachi Semiconductor – 4-bit HMCS400-Series microcomputer

HD404369 Series
$000
Bit 3
IM0
(IM of INT₀)
$001
IMTA
(IM of timer A)
$002
IMTC
(IM of timer C)
$003
IMS
(IM of serial)
Bit 2
IF0
(IF of INT₀)
IFTA
(IF of timer A)
IFTC
(IF of timer C)
IFS
(IF of serial)
Bit 1
RSP
(Reset SP bit)
IM1
(IM of INT₁)
IMTB
(IM of timer B)
IMAD
(IM of A/D)
Bit 0
IE
(Interrupt
enable flag)
IF1
(IF of INT₁)
IFTB
(IF of timer B)
IFAD
(IF of A/D)
Interrupt control bits area
$020
$021
Bit 3
DTON
(Direct transfer
on flag)
RAME
(RAM enable
flag)
Bit 2
ADSF
(A/D start flag)
IAOF
(I_AD off flag)
Bit 1
WDON
(Watchdog
on flag)
ICEF
(Input capture
error flag)
Bit 0
LSON
(Low speed
on flag)
ICSF
(Input capture
status flag)
$022
$023
Not used
Register flag area
IF: Interrupt request flag
IM: Interrupt mask
IE: Interrupt enable flag
SP: Stack pointer
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IE
IM
LSON
IAOF
IF
ICSF
ICEF
RAME
RSP
WDON
ADSF
DTON
Not used
SEM/SEMD
Allowed
Not executed
Not executed
Allowed
Allowed
Not executed in active mode
Used in subactive mode
Not executed
REM/REMD
Allowed
Allowed
Allowed
Not executed
Inhibited
Allowed
Not executed
TM/TMD
Allowed
Allowed
Inhibited
Inhibited
Allowed
Allowed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instuction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
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