HD404369 Datasheet, PDF (23/117 Pages) Hitachi Semiconductor – 4-bit HMCS400-Series microcomputer

HD404369 Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
INT₀
INT₁
Timer A Timer B Timer C A/D
IE
1
1
1
1
1
1
IF0 IM0
1
0
0
0
0
0
IF1 IM1
*
1
0
0
0
0
IFTA IMTA
*
*
1
0
0
0
IFTB IMTB
*
*
*
1
0
0
IFTC IMTC
*
*
*
*
1
0
IFAD IMAD
*
*
*
*
*
1
IFS IMS
*
*
*
*
*
*
Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.
Serial
1
0
0
0
0
0
0
1
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Figure 9 Interrupt Processing Sequence
Execution of
instruction at
start address
of interrupt
routine
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