H8SX1638 Datasheet, PDF (779/1164 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 18 I²C Bus Interface 2 (IIC2)
Initial
Bit
Bit Name Value R/W
Description
5
RDRF
0
R/W
Receive Data Register Full
[Setting condition]
• When receive data is transferred from ICDRS to
ICDRR
[Clearing conditions]
• When 0 is written to this bit after reading RDRF = 1
(When the CPU is used to clear this flag by writing
0 while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
• When data is read from ICDRR
4
NACKF 0
R/W
No Acknowledge Detection Flag
[Setting condition]
• When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER
is set to 1
[Clearing condition]
• When 0 is written to this bit after reading NACKF =
1
(When the CPU is used to clear this flag by writing
0 while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
3
STOP
0
R/W
Stop Condition Detection Flag
[Setting condition]
• When a stop condition is detected after frame
transfer
[Clearing condition]
• When 0 is written to this bit after reading STOP = 1
(When the CPU is used to clear this flag by writing
0 while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
Rev. 2.00 Sep. 10, 2008 Page 751 of 1132
REJ09B0364-0200