H8SX1638 Datasheet, PDF (527/1164 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 13 16-Bit Timer Pulse Unit (TPU)
Table 13.23 TIORL_0
Description
Bit 3 Bit 2 Bit 1 Bit 0 TGRC_0
IOC3 IOC2 IOC1 IOC0 Function TIOCC0 Pin Function
0
0
0
0
Output Output disabled
0
0
0
1
compare
register*²
Initial output is 0 output
0 output at compare match
0
0
1
0
Initial output is 0 output
1 output at compare match
0
0
1
1
Initial output is 0 output
Toggle output at compare match
0
1
0
0
Output disabled
0
1
0
1
Initial output is 1 output
0 output at compare match
0
1
1
0
Initial output is 1 output
1 output at compare match
0
1
1
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
Capture input source is TIOCC0 pin
capture _{Input capture at rising edge}
register*²
1
0
0
1
Capture input source is TIOCC0 pin
Input capture at falling edge
1
0
1
X
Capture input source is TIOCC0 pin
Input capture at both edges
1
1
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down*¹
[Legend]
X:
Don't care
Note: 1. When the bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and Pφ/1 is used as the
count clock of TCNT_1, this setting is invalid and input capture is not generated.
2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 2.00 Sep. 10, 2008 Page 499 of 1132
REJ09B0364-0200