H8SX1638 Datasheet, PDF (134/1164 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 6 Exception Handling
Bφ
Vector fetch
*
*
Internal First instruction
operation prefetch
*
RES
Address bus
(1)
(3)
(5)
RD
HWR, LWR
D15 to D0
High
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5) = (2)(4))
(6) First instruction in the exception handling routine
Note: * Seven program wait cycles are inserted.
Figure 6.2 Reset Sequence
(16-Bit External Access in On-chip ROM Disabled Advanced Mode)
Rev. 2.00 Sep. 10, 2008 Page 106 of 1132
REJ09B0364-0200