H8SX1638 Datasheet, PDF (739/1164 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 17 Serial Communication Interface (SCI, IrDA, CRC)
17.7.2 Data Format (Except in Block Transfer Mode)
Figure 17.25 shows the data transfer formats in smart card interface mode.
• One frame contains 8-bit data and a parity bit in asynchronous mode.
• During transmission, at least 2 etu (elementary time unit: time required for transferring one bit)
is secured as a guard time after the end of the parity bit before the start of the next frame.
• If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu
has passed from the start bit.
• If an error signal is sampled during transmission, the same data is automatically re-transmitted
after at least 2 etu.
In normal transmission/reception
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Output from the transmitting station
When a parity error is generated
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
[Legend]
Ds:
D0 to D7:
Dp:
DE:
Start bit
Data bits
Parity bit
Error signal
Output from the transmitting station
Output from
the receiving station
Figure 17.25 Data Formats in Normal Smart Card Interface Mode
For communication with the smart cards of the direct convention and inverse convention types,
follow the procedure below.
(Z)
A ZZ A ZZ ZAA Z
(Z) state
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Figure 17.26 Direct Convention (SDIR = SINV = O/E = 0)
Rev. 2.00 Sep. 10, 2008 Page 711 of 1132
REJ09B0364-0200