H8SX1638 Datasheet, PDF (250/1164 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 9 Bus Controller (BSC)
(2) 16-Bit 3-State Access Space
Figures 9.17 to 9.19 show the bus timing of 16-bit 3-state access space.
When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even
addresses, and the lower byte data bus (D7 to D0) is used for odd addresses. Wait cycles can be
inserted.
Read
Bφ
Address
CSn
AS
RD
D15 to D8
D7 to D0
Bus cycle
T₁
T₂
T₃
Valid
Invalid
Write
LHWR
LLWR
D15 to D8
D7 to D0
BS
RD/WR
High level
Valid
High-Z
DACK
Notes: 1. n = 0 to 7
2. When RDNn = 0
3. When DKC = 0
Figure 9.17 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address)
Rev. 2.00 Sep. 10, 2008 Page 222 of 1132
REJ09B0364-0200