H8SX1638 Datasheet, PDF (364/1164 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 10 DMA Controller (DMAC)
Figure 10.32 shows an example of block transfer mode activated by the DREQ signal low level.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the write cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
Bus released
1-block transfer
DMA read
cycle
DMA write
cycle
Bus released
1-block transfer
DMA read
cycle
DMA write
cycle
Bus released
Bφ
DREQ
Address bus
DMA
operation
Wait
Channel
Request
Transfer
source
Read
Write
Transfer
destination
Wait
Duration of transfer
request disabled
Request
Transfer
source
Read
Write
Transfer
destination
Wait
Duration of transfer
request disabled
Min. of 3 cycles
Min. of 3 cycles
[1] [2]
[3]
[4] [5]
[6]
[7]
Transfer request enable resumed
Transfer request enable resumed
[1] After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed after completion of the write cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
Figure 10.32 Example of Transfer in Block Transfer Mode Activated
by DREQ Low Level
Rev. 2.00 Sep. 10, 2008 Page 336 of 1132
REJ09B0364-0200