H8SX1638 Datasheet, PDF (585/1164 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 13 16-Bit Timer Pulse Unit (TPU)
13.10.11 Conflict between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 13.54 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
Pφ
TCNT input
clock
TCNT
Counter clear
signal
TGF flag
TCFV flag
H'FFFF
Disabled
H'0000
Figure 13.54 Conflict between Overflow and Counter Clearing
13.10.12 Conflict between TCNT Write and Overflow/Underflow
If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write
cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.
Figure 13.55 shows the operation timing when there is conflict between TCNT write and
overflow.
TGR write cycle
T₁
T₂
Pφ
Address
TCNT address
Write
TCNT
H'FFFF
TCNT write data
M
TCFV flag
Figure 13.55 Conflict between TCNT Write and Overflow
Rev. 2.00 Sep. 10, 2008 Page 557 of 1132
REJ09B0364-0200