HN58C1001 Datasheet, PDF (7/24 Pages) Hitachi Semiconductor – 1M EEPROM (128-kword x 8-bit) Ready/Busy and RES function

HN58C1001 Series
Write Cycle
Parameter
Symbol Min*² Typ Max Unit Test conditions
Address setup time
t_AS
0


ns
Address hold time
t_AH
150 

ns
CE to write setup time (WE controlled)
t_CS
0


ns
CE hold time (WE controlled)
t_CH
0


ns
WE to write setup time (CE controlled)
t_WS
0


ns
WE hold time (CE controlled)
t_WH
0


ns
OE to write setup time
t_OES
0


ns
OE hold time
t_OEH
0


ns
Data setup time
t_DS
100 

ns
Data hold time
t_DH
10


ns
WE pulse width (WE controlled)
t_WP
250 

ns
CE pulse width (CE controlled)
t_CW
250 

ns
Data latch time
t_DL
300 

ns
Byte load cycle
t_BLC
0.55 
30
µs
Byte load window
Write cycle time
t_BL
100 

µs
t_WC
—

10*³ ms
Time to device busy
Write start time
t_DB
120 

ns
t_DW
150*⁴ 

ns
Reset protect time
Reset high time*⁵
t_RP
100 

µs
t_RES
1


µs
Notes: 1. t_DF and t_DFR are defined as the time at which the outputs achieve the open circuit conditions and are
no longer driven.
2. Use this device in longer cycle than this value.
3. t_WC must be longer than this value unless polling techniques or RDY/Busy are used. This device
automatically completes the internal write operation within this value.
4. Next read or write operation can be initiated after t_DW if polling techniques or RDY/Busy are used.
5. This parameter is sampled and not 100% tested.
6. A7 to A16 are page addresses and must be same within the page write operation.
7. See AC read characteristics.
Rev.8.00, Nov. 27.2003, page 7 of 21