HN58C1001 Datasheet, PDF (22/24 Pages) Hitachi Semiconductor – 1M EEPROM (128-kword x 8-bit) Ready/Busy and RES function

Revision History
HN58C1001 Series Data Sheet
Rev. Date
Contents of Modification
Page Description
0.0 Jul. 11. 1991  Initial issue
1.0 Jan. 10. 1992 
5
6
16
8
Recommended DC Operating Conditions
Addition of VH
DC Characteristics
ICC3 max: 40 mA to 50 mA
ICC3 test: Cycle = 200 ns to Cycle = 150 ns
VIH max: VCC + 1 V to VCC + 0.3 V
VH min: VCC − 1.0 V to VCC − 0.5 V
AC Characteristics
Change of Test Conditions
Reference level: 1.8 V to 2.0 V
tDL min: 200 ns to 300 ns
tBLC min: 0.35 µs to 0.55 µs
tWP/tCW min: 150 ns to 250 ns
tCS/tCH to tWS/tWH (CE Controlled)
Functional Description
Deletion of Write Protection (2)
Data Protection 2:
during programming because to during
programming and read because
unprogrammable, standby or readout state to
unprogrammable state
Deletion of protection of mistake
by CE = VCC or OE = Low or
WE = VCC level at VCC on/off
Software data protection
Address: AAAA to AAAA or 2AAA
Change of Timing Waveforms
2.0 Jan. 21. 1993 
6




Deletion of HN58C1001-12
AC Characteristics
tDH min: 0 ns to 10 ns
Deletion of Mode Description
Addition of Reset function
Change of erase/write cycles in page mode: 10⁵ to 10⁴
Change of erase/write cycles in byte mode: 104 to 10³
3.0 Apr. 23. 1993 14 Addition of Toggle Bit
4.0 Nov. 25. 1994 6
6
11
Capacitance
Addition of note 1
AC Characteristics
Write cycle: Addition of note 2,3
Addition of tDW min: 150 ns
Page write timing waveform
Addition of note 1
5.0 May. 23. 1995  Deletion of HN58C1001R series (TFP-32DAR)