HN58C1001 Datasheet, PDF (16/24 Pages) Hitachi Semiconductor – 1M EEPROM (128-kword x 8-bit) Ready/Busy and RES function

HN58C1001 Series
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 128 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 127 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When
CE or WE is kept high for 100 µs after data input, the EEPROM enters write mode automatically and the
input data are written into the EEPROM.
Data Polling
Data polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a
write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM
is performing a write operation.
RDY/Busy Signal
RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to V_OL after the first write signal. At the end of write cycle,
the RDY/Busy signal changes state to high impedance.
RES Signal
When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping
RES low when V_CC is switched. RES should be high during read and programming because it doesn’t provide
a latch function.
V_CC
Read inhibit
Read inhibit
4-5
Program inhibit
Program inhibit
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising
edge of WE or CE.
Rev.8.00, Nov. 27.2003, page 16 of 21