32176 Datasheet, PDF (689/742 Pages) Renesas Technology Corp – 32-BIT RISC SINGLE-CHIP MICROCOMPUTER

21
(7) TCLK
Symbol
Timing
requirements
tw(TCLKH)
tw(TCLKL)
ELECTRICAL CHARACTERISTICS
21.9 A.C. Characteristics (when VCCE = 3.3 V)
Parameter
TCLK Input "H" Pulse Width
TCLK Input "L" Pulse Width
Rated Value
MIN
7×
tc(BCLK)
2
7×
tc(BCLK)
2
MAX
Unit See Fig.
21.9.7
ns
[99]
ns [100]
[99] tw(TCLKH)
TCLK
0.2VCCE
0.8VCCE
[100] tw(TCLKL)
Figure 21.9.7 TCLK Timing
(8) Read and write timing (1/4)
Symbol
Parameter
Rated Value
MIN
MAX
tsu(D-BCLKH)
Data Input Setup Time before BCLK
th(BCLKH-D)
Data Input Hold Time after BCLK
tsu(WAITL-BCLKH) WAIT# Input Setup Time before BCLK
th(BCLKH-WAITL) WAIT# Input Hold Time after BCLK
tsu(WAITH-BCLKH) WAIT# Input Setup Time before BCLK
th(BCLKH-WAITH) WAIT# Input Hold Time after BCLK
tc(BCLK)
BCLK Output Cycle Time
tw(BCLKH)
BCLK Output "H" Pulse Width
tw(BCLKL)
BCLK Output "L" Pulse Width
td(BCLKH-A)
Address Delay Time after BCLK
td(BCLKH-CS)
Chip Select Delay Time after BCLK
tv(BCLKH-A)
Address Valid Time after BCLK
tv(BCLKH-CS)
Chip Select Valid Time after BCLK
td(BCLKL-RDL)
tv(BCLKH-RDL)
td(BCLKL-BLWL)
td(BCLKL-BHWL)
tv(BCLKL-BLWL)
tv(BCLKL-BHWL)
td(BCLKL-D)
tv(BCLKH-D)
tpzx(BCLKL-DZ)
tpxz(BCLKH-DZ)
Read Delay Time after BCLK
Read Valid Time after BCLK
Write Delay Time after BCLK
Write Valid Time after BCLK
Data Output Delay Time after BCLK
Data Output Valid Time after BCLK
Data Output Enable Time after BCLK
Data Output Disable Time after BCLK
26
0
26
0
26
0
tc(BCLK)
2
-5
tc(BCLK)
2
-5
-11
-11
-12
-12
-16
-19
tc(XIN)
2
29
30
14
14
18
5
Unit See Figs.
21.9.8
21.9.9
ns
[31]
ns
[32]
ns
[33]
ns
[34]
ns
[78]
ns
[79]
ns
[16]
ns
[17]
ns
[18]
ns
[19]
ns
[20]
ns
[21]
ns
[22]
ns
[23]
ns
[24]
ns
[25]
ns
[26]
ns
[27]
ns
[28]
ns
[29]
ns
[30]
32176 Group Hardware Manual
Rev.1.10 REJ09B0067-0110 Jun 20.06
21-41