32176 Datasheet, PDF (291/742 Pages) Renesas Technology Corp – 32-BIT RISC SINGLE-CHIP MICROCOMPUTER

10
MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
<Count clock-dependent delay>
• Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is
generated by the time when the timer actually starts operating after writing to the enable bit. In operation
mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent
delay before the F/F output is inverted.
Write to the enable bit
BCLK
Count clock
Count clock period
Enable
F/F operation (Note 1)
Count clock-dependent
delay
Inverted
Note 1: This applies to the case where F/F output is inverted when the timer is enabled.
Figure 10.3.2 Count Clock Dependent Delay
32176 Group Hardware Manual
Rev.1.10 REJ09B0067-0110 Jun 20.06
10-45