32176 Datasheet, PDF (309/742 Pages) Renesas Technology Corp – 32-BIT RISC SINGLE-CHIP MICROCOMPUTER

10
MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
In the example below, the reload register is initially set to H’FFF8. When the timer starts, the value that "the
reload register -1" is loaded into the counter, letting it start counting down. In the diagram below, the value
H’0014 is written to the correction register when the counter has counted down to H’FFF0. As a result of this
correction, the count overflows to H’0004 and the counter fails to count correctly. Also, an interrupt request
is generated for an erroneous overflowed count.
Enabled
(by writing to the enable bit
or by external input)
Count clock
Enable bit
Write to the
correction register
(Note 1)
H'(FFF0+0014)
Overflow occurs
H'FFFF
H'FFF8
Counter
Undefined
value
H'FFFF
H'(FFF8-1)
H'FFF0
(Note 2)
Actual count after overflow
H'0004
H'0000
Reload register
Correction register
H'FFF8
Undefined
H'0014
F/F output
Data inverted
by enable
Data inverted
by underflow
TOP interrupt request
due to underflow
Note 1: A count clock dependent delay is included before F/F output changes state after the timer is enabled.
Note 2: The value that "reload register - 1" is reloaded.
Note: • This diagram does not show detailed timing information.
Figure 10.3.11 Example of an Operation in TOP Single-shot Output Mode Where Count Overflows Due to Correction
32176 Group Hardware Manual
Rev.1.10 REJ09B0067-0110 Jun 20.06
10-63