32176 Datasheet, PDF (313/742 Pages) Renesas Technology Corp – 32-BIT RISC SINGLE-CHIP MICROCOMPUTER

10
MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respec-
tively. When the timer is enabled, the counter starts counting down and at the cycle after the first underflow,
the counter is loaded with the content of "the reload register -1" and continues counting down. In the dia-
gram below, the value H’0008 is written to the correction register when the counter has counted down to
H’9000. As a result of this correction, the counter has its count value increased to H’9008 and counts
(H’F000 + 1 + H’0008 + 1) after the first underflow before it stops.
Enabled
(by writing to the enable bit
or by external input)
Underflow
(first time)
Underflow
(second time)
Count clock
Enable bit
Write to the
correction register
H'FFFF
H'(F000+0008+1)
H'F000
Counter
H'A000
H'9000+H'0008
H'9000
(Note 1)
H'0000
Reload register
H'F000
Correction register
Undefined
H'0008
F/F output
TOP interrupt request
due to underflow
Data inverted
by underflow
Data inverted
by underflow
Note 1: The value that "reload register - 1" is reloaded.
Note: • This diagram does not show detailed timing information.
Figure 10.3.15 Typical Operation in TOP Delayed Single-shot Output Mode when Count is Corrected
32176 Group Hardware Manual
Rev.1.10 REJ09B0067-0110 Jun 20.06
10-67