32176 Datasheet, PDF (636/742 Pages) Renesas Technology Corp – 32-BIT RISC SINGLE-CHIP MICROCOMPUTER

19
JTAG
19.4 Basic Operation of JTAG
19.4.4 Inspecting and Setting Data Registers
To inspect or set the data register, follow the procedure described below.
(1) To access the test access port (JTAG) for the first time, apply a test reset (to initialize the test circuit).
One of the following two methods may be used to apply a test reset:
• Pull the JTRST pin "L."
• Drive the JTMS pin "H" to apply 5 or more JTCK cycles
(2) Apply JTMS = "L" to enter the Run-Test/Idle state. To continue the idle state, hold JTMS input "L."
(3) Apply JTMS = "H" to exit the Run-Test/Idle state and perform IR path sequence. In the IR path se-
quence, specify the data register to inspect or set.
(4) Proceed to perform DR path sequence. Feed setup data from the JTDI pin into the data register speci-
fied in the IR path sequence, and read out reference data from the JTDO pin.
(5) To proceed to perform IR path or DR path sequence after the DR path sequence is completed, apply
JTMS = "H" to return to the Select-DR-Scan state.
To wait for the next processing after a series of IR and DR sequence processing is completed, apply
JTMS = "L" to enter the Run-Test/Idle state and keep that state.
TAP states ^{Test-Logic- Run-Test IR path}
DR path Run-Test IR path
DR path
Reset state /Idle state sequence sequence /Idle state sequence sequence
JTDI
(Note 1)
Instruction
code
Setup data
#0
#0
Instruction
code
Setup data
#1
#1
JTDO
(Note 2)
Fixed value
b'110001 ^{(Note 3)}
Fixed value
b'110001
(Note 3)
Specify the data register
to inspect or set.
(1) Basic access
Setup data is serially fed from JTDI.
Reference data is serially output from JTDO.
TAP states ^{Test-Logic- Run-Test}
Reset state /Idle state
IR path DR path
sequence sequence
Run-Test
/Idle state
DR path
sequence
DR path
sequence
JTDI
(Note 1)
Instruction
code
Setup data
#0
#0
Setup data Setup data
#1
#2
JTDO
(Note 2)
Fixed value
b'110001
(Note 3)
(Note 3) (Note 3)
Specify the data register
to inspect or set.
The same data register can be successively
operated on to set or inspect.
(2) Successive accesses to the same data register
Note 1: The setup value for each register must be supplied to the JTDI pin beginning with the LSB.
Note 2: The value in each register is output to the JTDO pin beginning with the LSB. It is only in the Shift-IR state of IR path
sequence and the Shift-DR state of DR path sequence that valid data is output from the JTDO pin. In all other states,
the JTDO pin goes to a high-impedance state.
Note 3: This shows readout from the data register selected by the instruction that was set in the immediately preceding IR path
sequence. The value sampled during Capture-DR state is output at the shift register stage of the selected data register.
Figure 19.4.5 Successive JTAG Access
32176 Group Hardware Manual
Rev.1.10 REJ09B0067-0110 Jun 20.06
19-10