32176 Datasheet, PDF (105/742 Pages) Renesas Technology Corp – 32-BIT RISC SINGLE-CHIP MICROCOMPUTER

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EIT
4.9 Interrupt Processing
4.9.3 External Interrupt (EI)
An external interrupt is generated upon an interrupt request which is output by the microcomputer’s internal
interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority
levels. For details, see Chapter 5, “Interrupt Controller.” For details about the interrupt request sources, see
each section in which the relevant internal peripheral I/O is described.
[Occurrence Conditions]
External interrupts are managed by the microcomputer’s internal interrupt controller based on interrupt
requests from each internal peripheral I/O, and are sent to the CPU via the interrupt controller. The CPU
checks these interrupt requests at a break in instructions residing on word boundaries, and when an
interrupt request is detected and the PSW register IE flag = "1", accepts it as an external interrupt.
In no case will an external interrupt be activated immediately after executing a 16-bit instruction that starts
from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately
after branching.)
Order in which instructions are executed
Address 1000 Address 1002 Address 1004
16-bit instruction 16-bit instruction
32-bit instruction
Address 1008
×
Interrupt may Interrupt cannot Interrupt may
be accepted be accepted be accepted
Figure 4.9.2 Timing at Which External Interrupt (EI) is Accepted
Interrupt may
be accepted
32176 Group Hardware Manual
Rev.1.10 REJ09B0067-0110 Jun 20.06
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