32176 Datasheet, PDF (443/742 Pages) Renesas Technology Corp – 32-BIT RISC SINGLE-CHIP MICROCOMPUTER

12
SERIAL INTERFACE
12.4 Receive Operation in CSIO Mode
12.4.4 About Successive Reception
If the following conditions are met when data reception has finished, data may be received successively.
• The receive enable bit is set to "1".
• Transmit conditions are met.
• No overrun error has occurred.
CSIO receive operation
starts
Receive conditions ^No
met?
Yes
Receive data
Overrun error ?
Yes
No
Set the SIO Receive Control Register
reception finished bit to "1"
Set the SIO Receive Control Register
overrun error and receive error sum bits to "1"
Store the received data
in the receive buffer register
End of CSIO receive
operation
Figure 12.4.2 Receive Operation during CSIO Mode (Hardware Processing)
32176 Group Hardware Manual
Rev.1.10 REJ09B0067-0110 Jun 20.06
12-35