SH7047F Datasheet, PDF (59/85 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7047 Series

Description of Registers Used (See example 1 for information on pins and port registers.)
Register
MBbuff
work
DTMR
DTSAR
DTDAR
DTCRA
DTCRB
DTC.DTBR
DTC.DTEF
HCAN_MCR
HCAN_IRR
HCAN_BCR0
HCAN_BCR1
HCAN_MB0.MC0
HCAN_MB0.MC4
HCAN_MB0.MC5
HCAN_MB0.LAFM15
HCAN_IMR
HCAN_MBIMR0
INTC.IPRK
HCAN_RXPR0
HCAN_IMR
Function
Initial Value
Storage area for received data base
―
address (H'FFFFD100).
Work register used for mailbox
―
initialization.
Increments both DTSAR and DTDAR
after transfer completes, sets block
transfer mode and byte transfer.
0xA890
Sets transfer source address as mailbox 0xFFFFB108
0 message data area.
Sets transfer destination address as
received data storage area.
0xFFFFD100
Sets number of block transfers (15).
0x000F
Sets block length (8 bytes).
0x0008
Sets top 16 bits of memory address at
which data transferred using DTC is
stored.
0xFFFF
Selects the interrupt source (RM1 in
HCAN-2) for starting DTC.
0x04
Clears reset request bit.
0x0000
Clears reset, hold, and sleep interrupt
flags. (To clear, write 1.)
0x0001
Sets bit rate to 250 kbps when φ is
50 MHz.
0x0009
0x4300
Sets data frame and standard format for 0x0000
mailbox 0.
Sets mailbox 0 as for reception.
0x03
Sets mailbox 0 reception size to a data 0x08
length of 8 bytes.
Sets identifier filter mask for mailbox 0. 0x7FF0
Enables message reception interrupts. 0xFFFD
Enables mailbox 0 interrupt requests. 0xFFFE
Sets priority of HCAN-2 interrupt
requests.
0x00F0
Clears mailbox 0 reception end flag.
(To clear, write 1.)
0x0001
Prohibits message reception interrupts. 0xFFFF
Module
Main routine
Reception
interrupt
routine
Rev. 1.00, 08/03, page 51 of 74