SH7047F Datasheet, PDF (20/85 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7047 Series

Table 2.2 DTC Function Allocation
Register
DTMR
DTSAR
DTDAR
DTCRA
DTCRB
DTBR
DTEF
Function
DTC mode register
Controls the DTC operation mode.
DTC source address register
Specifies the source address for data to be transferred using DTC.
DTC destination address register
Specifies the destination address for data to be transferred using DTC.
DTC transfer count register A
Specifies the number of DTC transfers.
DTC transfer count register B
In the block transfer mode, specifies the block length.
DTC database register
Specifies the top 16 bits of the memory address at which data transferred using
DTC is to be stored.
DTC enable register
Selects the interrupt source (RM1 in HCAN-2) for starting DTC.
Rev. 1.00, 08/03, page 12 of 74