SH7047F Datasheet, PDF (46/85 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7047 Series

• The data from mailboxes 1 to 15 is transmitted in a single batch.
• The transmission end flag is polled while transmission is in progress.
• After confirmation that the transmission end flag has been set, the transmission end flag is
cleared, completing the operation.
Reception Specifications
• Mailbox 0 is used.
• Identifiers are not masked and all transmissions are received.
• The message reception interrupt (IRR1) is used.
(a) When data is received DTC is triggered by the message reception interrupt, and the
received data is stored in on-chip RAM.
(b) Block transfer mode is used for DTC transfers. Fifteen blocks are transferred, with each
block containing 8 bytes of data.
(c) After the DTC transfers are completed, the reception end flag is cleared and message
reception interrupts are prohibited within the message reception interrupt routine,
completing the operation.
4.2 Transmission and Reception Specifications, Function Description
Tables 4.2 and 4.3 list the functions allocated to registers. (See example 1 for information on pins
and port registers.)
Rev. 1.00, 08/03, page 38 of 74