SH7047F Datasheet, PDF (23/85 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7047 Series

Description of Registers Used (See example 1 for information on pins and port registers.)
Register
work
HCAN_MCR
HCAN_IRR
HCAN_BCR0
HCAN_BCR1
HCAN_MB1.MC0
HCAN_MB1.MC4
HCAN_MB1.MC5
HCAN_MB1.MD7
HCAN_MB1.MD8
HCAN_MB1.MD9
HCAN_MB1.MD10
HCAN_MB1.MD11
HCAN_MB1.MD12
HCAN_MB1.MD13
HCAN_MB1.MD14
HCAN_IMR
HCAN_MBIMR0
INTC.IPRK
HCAN_TXPR0
HCAN_TXACK0
HCAN_IMR
Function
Initial Value Module
Work register used for mailbox initialization. ―
Main routine
Clears reset request bit.
0x0000
Clears reset, hold, and sleep interrupt flags. 0x0001
(To clear, write 1.)
Sets bit rate to 250 kbps when φ is 50 MHz. 0x0009
0x4300
Sets data frame and standard format for
mailbox 1. Also sets identifier (H'555).
0x5550
Sets mailbox 1 as for transmission.
0x01
Sets mailbox 1 transmission size to a data
length of 8 bytes.
0x08
Sets mailbox 1 byte 1 transmission data
(H'55).
0x55
Sets mailbox 1 byte 2 transmission data
(H'66).
0x66
Sets mailbox 1 byte 3 transmission data
(H'77).
0x77
Sets mailbox 1 byte 4 transmission data
(H'88).
0x88
Sets mailbox 1 byte 5 transmission data
(H'99).
0x99
Sets mailbox 1 byte 6 transmission data
(H'AA).
0xAA
Sets mailbox 1 byte 7 transmission data
(H'BB).
0xBB
Sets mailbox 1 byte 8 transmission data
(H'FF).
0xFF
Enables mailbox empty interrupts.
0xFEFF
Enables mailbox 1 interrupt requests.
0xFFFD
Sets the priority of HCAN-2 interrupt requests. 0x00F0
Sets mailbox 1 to transmission wait status. 0x0002
Clears mailbox 1 transmission end flag.
(To clear, write 1.)
Prohibits mailbox empty interrupts.
0x0002
0xFFFF
Mailbox
empty
interrupt
routine
Rev. 1.00, 08/03, page 15 of 74