M66591GP_15 Datasheet, PDF (56/135 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

M66591GP
(1) PIPEB_EMP_OVR6 (PIPE6 Buffer Empty/Size-Error Interrupt) Bits (b6)
This bit indicates that the received data size exceeds the maximum packet size or that the buffers of PIPE6 are
empty.
(1) When the transfer direction IN:
When all data stored in the buffers of PIPE6 have been transmitted (buffer empty), this bit is set to “1”.
(2) When the transfer direction OUT:
When the data packet size which has been received has exceeded max packet size of PIPE6 (size over detect),
this bit is set to “1”. The PID [1:0] bits of the PIPE 6 Control Register is set to “1X” (STALL).
This bit is cleared to “0” by writing “0”. This bit is not cleared when the internal clock is not supplied (SCLK bit of
USB Transceiver Control Register 0 is “0”.).
Writing “1” to these bits has no affect.
(2) PIPEB_EMP_OVR5 (PIPE5 Buffer Empty/Size-Error Interrupt) Bits (b5)
This bit indicates that the received data size exceeds the maximum packet size or that the buffers of PIPE5 are
empty.
(1) When the transfer direction IN:
When all data stored in the buffers of PIPE5 have been transmitted (buffer empty), this bit is set to “1”.
(2) When the transfer direction OUT:
When the data packet size which has been received has exceeded max packet size of PIPE5 (size over detect),
this bit is set to “1”. The PID [1:0] bits of the PIPE 5 Control Register is set to “1X” (STALL).
This bit is cleared to “0” by writing “0”. This bit is not cleared when the internal clock is not supplied (SCLK bit of
USB Transceiver Control Register 0 is “0”.).
Writing “1” to these bits has no affect.
(3) PIPEB_EMP_OVR4 (PIPE4 Buffer Empty/Size-Error Interrupt) Bits (b4)
This bit indicates that the received data size exceeds the maximum packet size or that the buffers of PIPE4 are
empty.
(1) When the transfer direction IN:
When all data stored in the buffers of PIPE4 have been transmitted (buffer empty), this bit is set to “1”.
(2) When the transfer direction OUT:
When the data packet size which has been received has exceeded max packet size of PIPE4 (size over detect),
this bit is set to “1”. The PID [1:0] bits of the PIPE 4 Control Register is set to “1X” (STALL).
This bit is cleared to “0” by writing “0”. This bit is not cleared when the internal clock is not supplied (SCLK bit of
USB Transceiver Control Register 0 is “0”.).
Writing “1” to these bits has no affect.
(4) PIPEB_EMP_OVR3 (PIPE3 Buffer Empty/Size-Error Interrupt) Bits (b3)
This bit indicates that the received data size exceeds the maximum packet size or that the buffers of PIPE3 are
empty.
(1) When the transfer direction IN:
When all data stored in the buffers of PIPE3 have been transmitted (buffer empty), this bit is set to “1”.
(2) When the transfer direction OUT:
When the data packet size which has been received has exceeded max packet size of PIPE3 (size over detect),
this bit is set to “1”. The PID [1:0] bits of the PIPE 3 Control Register is set to “1X” (STALL).
This bit is cleared to “0” by writing “0”. This bit is not cleared when the internal clock is not supplied (SCLK bit of
USB Transceiver Control Register 0 is “0”.).
Writing “1” to these bits has no affect.
Rev.1.00 Nov. 30, 2004 page 54 of 131