M66591GP_15 Datasheet, PDF (42/135 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

M66591GP
2.20 INT Pin Configuration Register 1
„ INT Pin Configuration Register 1 (INTPinCfg1)
<Address: H’42>
b15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 b0
INTL INTA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
<H/W reset: H’0000>
<S/W reset: ->
<USB bus reset: ->
b
Bit name
Function
RW
15~2 Reserved. Set it to “0”.
1 INTL
0: Edge sense
“0” “0”
{{
Interrupt Output Sense
0 INTA
1: Level sense
0: Low Active
{{
Interrupt Output Polarity
1: High Active
(1) INTL (Interrupt Output Sense) Bit (b1)
This bit selects the interrupt signal output type.
When edge sense is selected, the interrupt signal is negated when the interrupt factors have been cleared. However,
when any other interrupt factor is not still cleared, the signal is asserted once again. The duration of negation is
650ns.
When level sense is selected, the signal is kept in asserted until all the interrupt factors are cleared.
(2) INTA (Interrupt Output Polarity) Bit (b0)
This bit sets the interrupt signal output polarity.
Rev.1.00 Nov. 30, 2004 page 40 of 131