M66591GP_15 Datasheet, PDF (103/135 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

M66591GP
3.6.2.4 Reading the buffer memory on the SIE side (CFIFO port reading direction)
Even in the “FRDY=0” state, when data cannot be read from the buffer memory, confirming the SBUSY bit in the
CFIFOSIE register and setting “1” for the TGL bit makes it possible for the controller to read and access data on the
SIE side.
When using this function, “PID=NAK” should be set and “SBUSY=0” confirmed, and then “TGL=1” written.
M66591 is then able to read data from the C_FIFO Port Register.
The INTR interrupt is generated by operation of the TGL bit. “1” should not be written for the TGL bit in the when
DCP is selected.
3.6.2.5 Clearing the buffer memory on the SIE side (CFIFO port writing direction)
Even in the “FRDY=0” state, when data cannot written to the buffer memory, M66591 can cancel data that is
waiting to be sent, by the SBUSY bit and the SCLR bit of the C_FIFO Port Control Register.
When using this function, “PID=NAK” should be set and “SBUSY=0” confirmed, and then “SCLR=1” written.
M66591 is then able to write new data from the C_FIFO Port Register.
The INTR and BEMP interrupt is generated by operation of the SCLR bit. “1” should not be written for the SCLR
bit when DCP is selected.
3.6.3 Timing at which the FIFO port can be accessed
3.6.3.1 Timing at which the FIFO port can be accessed when switching pipes
Figure 3.24 shows a diagram of the timing up to the point where the FRDY bit and DTLN [9:0] bit are determined
when the pipe specified by the FIFO port has been switched (the Current_PIPE [2:0] bits has been changed).
The same timing applies with respect to the C_FIFO port, when the ISEL bit is changed.
WR0-1_N
Current_PIPE
PIPEA
PIPEB
max 450ns
max 200ns
min 20ns
FRDY
PIPEA valid
Indefinite
PIPEB valid
CPU_DTLN
DMA_DTLN
PIPEA valid
Indefinite
PIPEB valid
Figure 3.24 Timing at which the FRDY and DTLN bits are determined after changing a pipe
The FRDY and DTLN hold timing after PIPE changed
FRDY = “L” transit timing after PIPE changed
The FRDY and DTLN valid timing after PIPE changed
: min 20ns
: max 200ns
: max 450ns
3.6.3.2 CPU_DTLN [9:0] and DMA_DTLN [9:0] timing when reading
Figure 3.25 shows a diagram of the timing up to the point when CPU_DTLN [9:0] bits and DMA_DTLN [9:0] bits
are confirmed at the operation of FIFO access when the RCNT bit of C_FIFO Port Control Register and D0_FIFO
Port Control Register is “1”.
RD_N
DTLN
min 0ns
min 150ns
valid
Indefinite
valid
Figure 3.25 CPU_DTLN and DMA_DTLN timing at reading
Rev.1.00 Nov. 30, 2004 page 101 of 131