M66591GP_15 Datasheet, PDF (32/135 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

M66591GP
2.15 C_FIFO Port Control Register 2
„ C_FIFO Port Control Register 2 (C_FIFOPortCtrl2)
<Address: H’2E>
b15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 b0
TGL SCLR SBUSY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
<H/W reset: H’0000>
<S/W reset: H’0000>
<USB bus reset: ->
b
Bit name
Function
RW
15 TGL
<When set to OUT buffer>
“0” {
Buffer Toggle
• Write
0: Invalid (Ignored when written)
1: Toggles access buffer
<When set to IN buffer>
• Write
Set it to “0”
14 SCLR
<When set to OUT buffer>
“0” {
Buffer Clear
• Write
0: Invalid (Ignored when written)
1: Inhibited
<When set to IN buffer>
• Write
0: Invalid (Ignored when written)
1: Clear the SIE side buffer
13 SBUSY
0: SIE no access state
{-
SIE side Buffer Busy
1: SIE access state
12~0 Reserved. Set it to “0”.
“0” “0”
(1) TGL (Buffer Toggle) Bit (b15)
The SIE side buffer is changed over to the CPU side buffer by writing “1” to this bit while the FIFO buffer is not full
in continuous transfer mode. At this time, the buffer ready interrupt occurs. This bit is valid only for the PIPE of OUT
direction. Further, when the PIPE which has been set to the Current_PIPE [2:0] bits of the C_FIFO Port Control
Register 0 is DCP, writing “1” to this bit is invalid.
Writing “0” to this bit is invalid.
Explanation of Terms: Refer to “1.5 Block Diagram” about “SIE side” and “CPU side”.
(2) SCLR (Buffer Clear) Bit (b14)
The SIE side buffer is cleared and the SIE side buffer is changed over to the CPU side buffer by writing “1” to this
bit. This bit is valid only for the PIPE of IN direction. Further, when the PIPE which has been set to the
Current_PIPE [2:0] bits of the C_FIFO Port Control Register 0 is DCP, writing “1” to this bit is invalid.
Please set according to the following procedures in order to use this bit:
(1) Set the PID [1:0] bits of the PIPE i Control Register corresponding to the PIPE having been set to the
Current_PIPE [2:0] bits of the C_FIFO Port Control Register 0 to the NAK so that it does not respond to the IN
transaction.
(2) Confirm that the SBUSY bit is “0”. (Confirm that no buffer access exists.)
(3) Clear the SIE-side buffer by writing “1” to the SCLR bit.
Writing “0” to this bit is invalid.
(3) SBUSY (SIE side Buffer Busy) Bit (b13)
This bit indicates that SIE is accessing the buffer of the PIPE having been set to the Current_PIPE [2:0] bits of the
C_FIFO Port Control Register 0. Further, when the PIPE which has been set to the Current_PIPE [2:0] bits is DCP,
reading of this bit is invalid.
Rev.1.00 Nov. 30, 2004 page 30 of 131