M66591GP_15 Datasheet, PDF(31/135 Page) Renesas Technology Corp

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M66591GP_15 Datasheet, PDF (31/135 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

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M66591GP

(2) When data have been written up to the MaxPacketSize in non-continuous transfer mode.

When the buffer becomes empty, this bit is cleared. Writing â0â to this bit is invalid.

Further, the PIPE having been set to the Current_PIPE [2:0] is DCP, the IN/OUT direction is determined by the

ISEL bit.

Note: When the PIPE having been set to the Current_PIPE [2:0] bits is IN and this bit is â1â, writing â1â to this

bit is prohibited.

(2) BCLR (Buffer Clear) Bit (b14)

When â1â is written to this bit, the buffer of the PIPE having been set to the Current_PIPE [2:0] bits is cleared.

Refer to â3.6.2.3 Buffer Clearâ for detail.

While the FRDY bit of the C_FIFO Port Control Register 1 is â1â, it enables writing â1â to this bit.

However, the PIPE having been set to the Current_PIPE [2:0] bits of the C_FIFO Port Control Register 0 is DCP,

the buffer having been selected by the ISEL bit is cleared irrespective of the FRDY bit. To clear the buffer of DCP, set

the PID [1:0] bits of DCP Control Register to the NAK before writing â1â to this bit.

Writing â0â to this bit is invalid.

(3) FRDY (C_FIFO Port Ready) Bit (b13)

The C_FIFO Port Register 0 can be accessed while â1â is set to this bit.

(4) CPU_DTLN [9:0] (C_FIFO Receive Data Length) Bits (b9-b0)

These bits indicate the receive data length.

When the RCNT bit of the C_FIFO Port Control Register 0 is â1â, every time the C_FIFO Port Register is read out,

these bits count down at -1 for 8-bit width and -2 for 16-bit width.

When the RCNT bit is â0â, the receive data length is retained also during reading data and these bits are cleared

after all the receive data are read out.

When the PIPE having been set to the Current_PIPE [2:0] bits of the C_FIFO Port Control Register 0 is IN

direction, these bits are invalid.

Further, when the PIPE having been set to the Current_PIPE [2:0] bits is DCP, these bits are valid only when the

ISEL bit is â1â.

Note: It is necessary to do polling FDRY and confirm FRDY = 1 before read these bits. Refer to â3.6 Buffer

Memoryâ for reading timing.

Rev.1.00 Nov. 30, 2004 page 29 of 131

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