M66591GP_15 Datasheet, PDF (130/135 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

M66591GP
4.9.20 DMA transfer read timing (when set to separate bus and burst transfer)
DREQ
31 _{tsur (A) thr (A) 34}
A7-1
Address is
established
Address is
established
CS_N
48
tw (cycle) ⁴⁷
tw (CTRL_B) _{trec (CTRL_B)} ⁴⁹
RD_N
Note 5-5
ta (A) ¹ tv (A) ²
3
ta (CTRL-D)
tv (CTRL-D) ⁴
D15-0
D0
D1
DEND
17
tdis (CTRL - Dreq)
Address is
established
Address is
established
Dn-1
11
ta (CTRL - DendV)
Dn
12
tv (CTRL - DendV)
Note 5-1: Writing through the combination of DACK, WR0_N and WR1_N is carried out during the overlap of active (Low).
The specification from the rising edge is valid from the earliest inactive signal.
The specification of pulse width becomes valid during the overlap of active (Low).
Note 5-2: Reading through the combination of DACK and RD_N is carried out during the overlap of active (Low).
The specification from the falling edge is valid from the latest active signal.
The specification from the rising edge is valid from the earliest inactive signal.
The specification of pulse width becomes valid during the overlap of active (Low).
Note 5-3: Writing/reading through the combination of DACK and DSTRB_N is carried out during the overlap of active
(Low).
The specification from the falling edge is valid from the latest active signal.
The specification from the rising edge is valid from the earliest inactive signal.
The specification of pulse width becomes valid during the overlap of active (Low).
Note 5-4: Writing through the combination of CS_N, WR0_N and WR1_N is carried out during the overlap of active (Low).
The specification from the rising edge is valid from the earliest inactive signal.
The specification of pulse width becomes valid during the overlap of active (Low).
Note 5-5: Reading through the combination of CS_N and RD_N is carried out during the overlap of active (Low).
The specification from the falling edge is valid from the latest active signal.
The specification from the rising edge is valid from the earliest inactive signal.
The specification of pulse width becomes valid during the overlap of active (Low).
Note 5-6: When the receipt data is one byte, the data determined time is "(23) td (DREQ-DV)" and the DEND determined
time is "(24)td(DREQ-DendV)".
Rev.1.00 Nov. 30, 2004 page 128 of 131