M66591GP_15 Datasheet, PDF (5/135 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

M66591GP
The pin functions of the M66591 are shown in Table 1.1.
Item
CPU
interface
Interrupt
interface
Pin Name
D15-D8
D7/AD7-D1/AD
1, D0
A7/ALE, A6-A1
CS_N
RD_N
WR1_N
WR0_N
MPBUS
INT
Table 1.1 Pin Functions of M66591
Input/Output Name / Function
Pin
Count
Input/Output Data Bus
8
These are data bus to access the registers from the CPU.
Input/Output Data Bus / Address Bus
8
When select to 16-bit separate bus, these pins are used as D7-D0 of data bus.
When select to 16-bit multiplex bus, D7-D0 input/output and AD7-AD1 input are
performed at time-sharing. In this case, AD0 is not used.
Input
Address Bus / Address Latch Enable
7
When select to 16-bit separate bus, these pins are address bus to access the
registers from the CPU.
When select to 16-bit multiplex bus, A7 becomes the ALE pin, latching addresses
at the falling edge. A6-A1 are not used.
Input
Chip Select
1
When this pin is low level, M66591 is selected.
Input
Read Strobe
1
Data are read from registers at low level.
Input
D15-D8 Byte Write Strobe
1
The data (D15-D8) are written to the registers at the rising edge.
Input
D7-0 Byte Write Strobe
1
The data (D7-D0) are written to the registers at the rising edge.
Input
Bus Mode Select
1
The 16-bit separate bus is selected at low level.
The 16-bit multiplex bus is selected at high level.
This pin should not be switched after H/W reset.
Output
Interrupt
1
Interrupts are requested to the CPU. Polarity of this pin can be selected by register
setting.
DMA
interface
USB
interface
SD7/PA7-SD0/ Input/Output
PA0
DREQ
Output
DACK
Input
DSTB_N
Input
DEND
Input/Output
DHP
DHM
DFP
DFM
Input/Output
Input/Output
Input/Output
Input/Output
Split Bus / General-purpose Port
8
These pins are used to select either split bus (DMA Interface) or general-purpose
port (GPIO).
DMA Request
1
This pin is used to request DMA transfer of the D0_FIFO port. Polarity of this pin
can be selected by register setting.
DMA Acknowledge
1
DMA transfer of the D0_FIFO port is enabled in either low or high level. Polarity of
this pin can be selected by register setting.
Split Bus Strobe
1
This pin is used as data strobe signal when the D0_FIFO port has been set to the
split bus (DMA Interface).
When the RWstb bit of the Data Pin & FIFO/DMA Control Pin Configuration
Register 2 is set to “1” (RD/WR strobe mode), this pin is used as data strobe signal.
Transfer Terminal
1
When the PIPE direction is “IN”, this pin receives transfer complete signal as an
input signal from any other peripheral chip or the CPU.
When the PIPE direction is “OUT”, this pin indicates the last data transferred as the
output signal. Polarity of this pin can be set by a register.
USB Hi-Speed Data
1
Connect the D+ signal of USB bus.
USB Hi-Speed Data
1
Connect the D- signal of USB bus.
USB Full-Speed Data
1
Connect this pin to DHP via a 43Ω 1% resistance.
USB Full-Speed Data
1
Connect this pin to DHM via a 43Ω 1% resistance.
Rev.1.00 Nov. 30, 2004 page 3 of 131