RX111_16 Datasheet, PDF (53/127 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory

RX111 Group
5. Electrical Characteristics
Table 5.7 DC Characteristics (5) (2/2)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVSS0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, T_a = –40 to +105°C
Item
Symbol
Typ
*⁴
Max
Unit
Test
Conditions
Supply
current*¹
Low-speed
operating mode
Normal
operating
mode
No peripheral operation*⁸ ICLK = 32.768 kHz I_CC
4.0 — μA
All peripheral operation:
Normal*^9, *¹⁰
ICLK = 32.768 kHz
11.5 —
All peripheral operation:
Max.*^9, *¹⁰
ICLK = 32.768 kHz
— 40
Sleep mode No peripheral operation*⁸ ICLK = 32.768 kHz
2.2 —
All peripheral operation:
Normal*⁹
ICLK = 32.768 kHz
7.1 —
Deep sleep
mode
No peripheral operation*⁸ ICLK = 32.768 kHz
All peripheral operation:
Normal*⁹
ICLK = 32.768 kHz
1.8 —
5.3
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs
are in the off state.
Note 2. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is PLL. FCLK and
PCLK are set to divided by 64.
Note 3. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is PLL. FCLK and PCLK
are set to the same frequency as ICLK.
Note 4. Values when VCC = 3.3 V.
Note 5. This is the increase for programming or erasure of the ROM or E2 DataFlash during program execution.
Note 6. Clock supply to the peripheral functions is stopped. The clock source is PLL when ICLK = 12 MHz, and HOCO otherwise. FCLK
and PCLK are set to divided by 64.
Note 7. Clocks are supplied to the peripheral functions. The clock source is PLL when ICLK = 12 MHz, and HOCO otherwise. FCLK and
PCLK are set to the same frequency as ICLK.
Note 8. Clock supply to the peripheral functions is stopped. The clock source is the sub-clock oscillator. FCLK and PCLK are set to
divided by 64.
Note 9. Clocks are supplied to the peripheral functions. The clock source is the sub-clock oscillator. FCLK and PCLK are set to the same
frequency as ICLK.
Note 10. Values when the MSTPCRA.MSTPA17 bit (12-bit A/D converter module stop bit) is set to “transition to the module stop state is
made”.
R01DS0190EJ0130 Rev.1.30
May 31, 2016
Page 53 of 127