PD46365084B Datasheet, PDF (5/39 Pages) Renesas Technology Corp – 36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD46365184B]
2M x 18
1
2
3
A CQ# VSS/144M A
B NC
Q9
D9
C NC
NC
D10
D NC
D11 Q10
E NC
NC
Q11
F NC
Q12
D12
G NC
D13 Q13
H DLL# VREF VDDQ
J NC
NC
D14
K NC
NC
Q14
L NC
Q15
D15
M NC
NC
D16
N NC
D17 Q16
P NC
NC
Q17
R TDO TCK
A
4
W#
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
5
BW1#
NC
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
6
7
8
9
10
11
K# NC/288M R#
K BW0# A
A
VSS/72M CQ
NC
NC
Q8
NC
A
VSS
NC
Q7
D8
VSS
VSS
VSS
NC
NC
D7
VSS
VSS
VDDQ
NC
D6
Q6
VSS
VDD
VDDQ
NC
NC
Q5
VSS
VDD
VDDQ
NC
NC
D5
VSS
VDD
VDDQ VDDQ
VREF
ZQ
VSS
VDD
VDDQ
NC
Q4
D4
VSS
VDD
VDDQ
NC
D3
Q3
VSS
VSS
VDDQ
NC
NC
Q2
VSS
VSS
VSS
NC
Q1
D2
A
A
VSS
NC
NC
D1
C
A
A
NC
D0
Q0
C#
A
A
A
TMS TDI
A
D0 to D17
Q0 to Q17
R#
W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V_REF
V_DD
V_DDQ
V_SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 7A and 10A are expansion addresses : 10A for 72Mb
: 10A and 2A for 144Mb
: 10A, 2A and 7A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 5 of 38