PD46365084B Datasheet, PDF (12/39 Pages) Renesas Technology Corp – 36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Truth Table
Operation
CLK R# W#
D or Q
WRITE cycle
L → H H L Data in
Load address, input write data on
Input data DA(A+0) DA(A+1) DA(A+2) DA(A+3)
consecutive K and K# rising edge
Input clock K(t+1) ↑ K#(t+1) ↑ K(t+2) ↑ K#(t+2) ↑
READ cycle
L → H L × Data out
Load address, read data on
Output data QA(A+0) QA(A+1) QA(A+2) QA(A+3)
consecutive C and C# rising edge
Output clock C#(t+1) ↑ C(t+2) ↑ C#(t+2) ↑ C(t+3) ↑
NOP (No operation)
L → H H H D = ×, Q = High-Z
Clock stop
Stopped × × Previous state
Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
except if C and C# are HIGH then data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
7. If R# was LOW to initiate the previous cycle, this signal becomes a don't care for this WRITE operation
however it is strongly recommended that this signal is brought HIGH as shown in the truth table.
8. W# during write cycle and R# during read cycle were HIGH on previous K clock rising edge. Initiating
consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The
device will ignore the second request.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
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