PD46365084B Datasheet, PDF (25/39 Pages) Renesas Technology Corp – 36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name Pin assignments
Description
TCK
2R
TMS
10R
TDI
11R
TDO
1R
Test Clock Input. All input are captured on the rising edge of TCK and all
outputs propagate from the falling edge of TCK.
Test Mode Select. This is the command input for the TAP controller state
machine.
Test Data Input. This is the input side of the serial registers placed between
TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP controller state machine and the instruction that is currently
loaded in the TAP instruction.
Test Data Output. This is the output side of the serial registers placed between
TDI and TDO. Output changes in response to the falling edge of TCK.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter
Symbol
Conditions
MIN.
JTAG Input leakage current
JTAG I/O leakage current
I_LI
0 V ≤ V_IN ≤ V_DD
I_LO
0 V ≤ V_IN ≤ V_DDQ,
Outputs disabled
−5.0
−5.0
JTAG input HIGH voltage
JTAG input LOW voltage
JTAG output HIGH voltage
JTAG output LOW voltage
V_IH
V_IL
V_OH1
V_OH2
V_OL1
V_OL2
| I_OHC | = 100 μA
| I_OHT | = 2 mA
I_OLC = 100 μA
I_OLT = 2 mA
1.3
−0.3
1.6
1.4
MAX.
+5.0
+5.0
V_DD+0.3
+0.5
0.2
0.4
Unit
μA
μA
V
V
V
V
V
V
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
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