PD46365084B Datasheet, PDF (23/39 Pages) Renesas Technology Corp – 36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Read and Write Timing
K
K#
R#
W#
Address
Data in
NOP
READ
WRITE
READ
WRITE
NOP
1
2
3
4
5
6
7
TKHKL TKLKH
TKHKH
TKHK#H TK#HKH
TIVKH
TKHIX
TIVKH
TKHIX
A0
TAVKH TKHAX
A1
A2
A3
TDVKH TKHDX
TDVKH TKHDX
D10
D11 D12 D13
D30
D31 D32 D33
Data out
CQ
CQ#
C
C#
Qx2 Qx3
TCHQX1
Q00
Q01 Q02
TCHQX TCHQX
TCHQV TCHQV
Q03 Q20
Q21 Q22
Q23
TCQHQX
TCHQZ
TCQHQV
TKHCH
TCHCQX
TCHCQV
TCHCQX
TCHCQV
TCQHCQ#H TCQ#HCQH
TKHKL TKLKH
TKHKH
TKHK#H TK#HKH
TKHCH
Remarks 1. Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2. Outputs are disabled (high impedance) 3.5 clock cycles after the last READ (R# = LOW) is input in the
sequences of [READ]-[NOP]-[NOP], [READ]-[WRITE]-[NOP] and [READ]-[NOP]-[WRITE].
3. In this example, if address A2 = A1, data Q20 = D10, Q21 = D11, Q22 = D12 and Q23 = D13.
Write data is forwarded immediately as read results.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 23 of 38