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PD46365084B Datasheet, PDF (1/39 Pages) Renesas Technology Corp – 36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION | |||
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μPD46365084B
μPD46365094B
μPD46365184B
μPD46365364B
Datasheet
36M-BIT QDRTM II SRAM
4-WORD BURST OPERATION
R10DS0090EJ0400
Rev.4.00
Nov 09 2012
Description
The μPD46365084B is a 4,194,304-word by 8-bit, the μPD46365094B is a 4,194,304-word by 9-bit, the
μPD46365184B is a 2,097,152-word by 18-bit and the μPD46365364B is a 1,048,576-word by 36-bit
synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-
transistor memory cell.
The μPD46365084B, μPD46365094B, μPD46365184B and μPD46365364B integrate unique synchronous
peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are
latched on the positive edge of K and K#. These products are suitable for application which require
synchronous operation, high speed, low voltage, high density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
⢠1.8 ± 0.1 V power supply
⢠165-pin PLASTIC BGA (13 x 15)
⢠HSTL interface
⢠PLL circuitry for wide output data valid window and future frequency scaling
⢠Separate independent read and write data ports with concurrent transactions
⢠100% bus utilization DDR READ and WRITE operation
⢠Four-tick burst for reduced address frequency
⢠Two input clocks (K and K#) for precise DDR timing at clock rising edges only
⢠Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
⢠Internally self-timed write control
⢠Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
⢠User programmable impedance output (35 to 70 Ω)
⢠Fast clock cycle time : 3.3 ns (300 MHz) , 4.0 ns (250 MHz)
⢠Simple control logic for easy depth expansion
⢠JTAG 1149.1 compatible test access port
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 1 of 38
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