PD46365084B Datasheet, PDF (27/39 Pages) Renesas Technology Corp – 36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
JTAG AC Characteristics (TA = 0 to 70°C)
Parameter
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Symbol
t_THTH
f_TF
t_THTL
t_TLTH
Conditions
MIN.
50
20
20
Output time
TCK LOW to TDO unknown
t_TLOX
0
TCK LOW to TDO valid
t_TLOV
Setup time
TMS setup time
t_MVTH
5
TDI valid to TCK HIGH
t_DVTH
5
Capture setup time
t_CS
5
Hold time
TMS hold time
t_THMX
5
TCK HIGH to TDI invalid
t_THDX
5
Capture hold time
t_CH
5
JTAG Timing Diagram
MAX.
20
Unit
ns
MHz
ns
ns
ns
10
ns
ns
ns
ns
ns
ns
ns
TCK
TMS
TDI
TDO
tMVTH
tTHTH
tTHTL
tTLTH
tTHMX
tDVTH
tTHDX
tTLOX
tTLOV
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 27 of 38