H8S2117 Datasheet, PDF (498/968 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.7 Interrupt Identification Register (FIIR)
FIIR consists of bits that identify interrupt sources. For details, see table 16.4.
Bit
Bit Name Initial Value R/W Description
7
FIFOE1 0
R
FIFO Enable 0, 1
6
FIFOE0 0
R
These bits indicate the transmit/receive FIFO setting.
00: Transmit/receive FIFOs disabled
11: Transmit/receive FIFOs enabled
5, 4 
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
3
INTID2 0
R
Interrupt ID2, ID1, ID0
2
INTID1 0
1
INTID0 0
R
These bits Indicate the interrupt of the highest
R
priority among the pending interrupts.
000: Modem status
001: FTHR empty
010: Receive data ready
011: Receive line status
110: Character timeout (when the FIFO is enabled)
0
INTPEND 1
R
Interrupt Pending
Indicates whether one or more interrupts are
pending.
0: Interrupt pending
1: No interrupt pending
Rev. 2.00 Feb. 20, 2008 Page 474 of 940
REJ09B0350-0200