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H8S2117 Datasheet, PDF (442/968 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series
Section 15 Serial Communication Interface (SCI)
15.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.3 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF. The
CPU can always read BRR. The CPU can write to BRR only at the initial settings; do not have the
CPU write to BRR in transmission, reception, and simultaneous data transmission and reception.
Table 15.3 Relationships between N Setting in BRR and Bit Rate B
Mode
Asynchronous mode
Bit Rate
φ × 106
B=
64 × 2 2n – 1× (N + 1)
Error
φ × 106
Error (%) = {
– 1 } × 100
B × 64 × 2 2n – 1× (N + 1)
Clocked synchronous mode
φ × 106

B=
8 × 22n – 1× (N + 1)
Smart card interface mode
φ × 106
B=
S × 2 2n + 1× (N + 1)
φ × 106
Error (%) =
{
B × S × 2 2n + 1× (N + 1)
–1 } × 100
[Legend]
B:
N:
φ:
n and S:
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Determined by the SMR settings shown in the following table
SMR Setting
CKS1
CKS0
n
0
0
0
0
1
1
1
0
2
1
1
3
SMR Setting
BCP1
BCP0
S
0
0
32
0
1
64
1
0
372
1
1
256
Table 15.4 shows sample N settings in BRR in normal asynchronous mode. Table 15.5 shows the
maximum bit rate settable for each frequency. Table 15.7 and 15.9 show sample N settings in
BRR in clocked synchronous mode and smart card interface mode, respectively. In smart card
interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected.
For details, see section 15.7.4, Receive Data Sampling Timing and Reception Margin. Tables 15.6
and 15.8 show the maximum bit rates with external clock input.
Rev. 2.00 Feb. 20, 2008 Page 418 of 940
REJ09B0350-0200