H8S2117 Datasheet, PDF (343/968 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 11 16-Bit Cycle Measurement Timer (TCM)
(3) CMF Set Timing when a Compare Match occurs
The CMF flag in TCMCSR is set in the last state where the values in TCMCNT and TCMMLCM
match in timer mode. Therefore, a compare match signal is not generated until a further cycle of
the TCMCNT input clock is generated after a match between the values in TCMCNT and
TCMMLCM. For details, see section 11.6.2, Conflict between TCMMLCM Write and Compare
Match. Figure 11.6 shows the timing with which the CMF flag is set.
φ
TCMCNT
N
TCMMLC
Compare match
signal
CMF
N+1
N
Figure 11.6 Timing of CMF Flag Setting on a Compare Match
11.4.2 Cycle Measurement Mode
When the TCMMDS bit in TCMCR is set to 1, the TCM operates in cycle measurement mode.
(1) Counter Operation
Setting the TCMMDS bit in TCMCR to 1 selects cycle measurement mode, in which counting up
proceeds regardless of the setting of the CST bit in TCMCR. TCMCNT is cleared to H'0000 on
detection of the first edge in the measurement period and counts up from there. Figure 11.7 shows
an example of counter operation in cycle measurement mode.
φ
TCMCYI
TCMCNT
clear signal
TCMCNT
input clock
TCMCNT
N
H'0000
H'0001
H'0002
H'0003 H'0000 H'0001
Figure 11.7 Example of Counter Operation in Cycle Measurement Mode
Rev. 2.00 Feb. 20, 2008 Page 319 of 940
REJ09B0350-0200