H8S2117 Datasheet, PDF (257/968 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 9 14-Bit PWM Timer (PWMX)
1 conversion cycle
t_f1
t_f2
t_f255
t_f256
t_H1
t_H2
t_H3
t_f1 = t_f2 = t_f3 = ··· = t_f255 = t_f256 = T× 64
t_H1 + t_H2 + t_H3 + ··· + t_H255 + t_H256 = T_H
t_H255
(a) CFS = 0 [base cycle = resolution (T) × 64]
t_H256
1 conversion cycle
t_f1
t_f2
t_f63
t_f64
t_H1
t_H2
t_H3
t_H63
t_H64
t_f1 = t_f2 = t_f3 = ··· = t_f63 = t_f64 = T× 256
t_H1 + t_H2 + t_H3 + ··· + t_H63 + t_H64 = T_H
(b) CFS = 1 [base cycle = resolution (T) × 256]
Figure 9.5 Output Waveform (OS = 1, DADR corresponds to T_H)
An example of the additional pulses when CFS = 1 (base cycle = resolution (T) × 256) and OS = 1
(inverted PWM output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in
DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0)
determine the locations of the additional pulses as shown in figure 9.6.
Table 9.6 lists the locations of the additional pulses.
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS
Duty cycle of base pulse
Location of additional pulses
1
1
Figure 9.6 D/A Data Register Configuration when CFS = 1
Rev. 2.00 Feb. 20, 2008 Page 233 of 940
REJ09B0350-0200