M32C85 Datasheet, PDF (471/542 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/85 Group (M32C/85, M32C/85T)
26. Electrical Characteristics (M32C/85)
VCC1=VCC2=3.3V
Switching Characteristics
(VCC1=VCC2=3.0 to 3.6V, VSS = 0V at Topr = –20 to 85^oC unless otherwise specified)
Table 26.40 Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space)
Symbol
Parameter
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(DB-WR)
th(WR-DB)
tw(WR)
Address Output Delay Time
Address Output Hold Time (BCLK standard)
Address Output Hold Time (RD standard)⁽³⁾
Address Output Hold Time (WR standard)⁽³⁾
Chip-Select Signal Output Delay Time
Chip-Select Signal Output Hold Time (BCLK standard)
Chip-Select Signal Output Hold Time (RD standard)⁽³⁾
Chip-Select Signal Output Hold Time (WR standard)⁽³⁾
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (WR standard)
Data Output Hold Time (WR standard)⁽³⁾
WR Output Width
Measurement
Condition
Standard
Unit
Min.
Max.
18
ns
0
ns
0
ns
(Note 1)
ns
18
ns
0
ns
See Figure 26.2 ₀
ns
(Note 1)
ns
18
ns
-3
ns
18
ns
0
ns
(Note 2)
ns
(Note 1)
ns
(Note 2)
ns
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
th(WR – DB) =
10 ⁹
– 20 [ns]
f(BCLK) X 2
th(WR – AD) =
10 ⁹
– 10 [ns]
f(BCLK) X 2
th(WR – CS) =
10 ⁹
– 10 [ns]
f(BCLK) X 2
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles.
tw(WR) =
10⁹x n
f(BCLK) X 2 ^{– 15 [ns] (if external bus cycle is aφ + bφ, n=(b x 2)-1)}
td(DB – WR) =
9
10 x m
f(BCLK)
– 20
[ns] (if external bus cycle is aφ + bφ, m=b)
3. tc ns is added when recovery cycle is inserted.
Rev. 1.03 Jul. 01, 2005 ^{Page 448} of 494
REJ09B0037-0103