M32C85 Datasheet, PDF (172/542 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/85 Group (M32C/85, M32C/85T)
14. DMACII
14.3.2 Immediate Data Transfer
DMAC II transfers immediate data to any memory location. A fixed or relocatable address can be se-
lected as the destination address. Store the immediate data into SADR. To transfer an 8-bit immediate
data, write the data in the low-order byte of SADR (high-order byte is ignored).
14.3.3 Calculation Transfer
After two memory data or an immediate data and memory data are added together, DMAC II transfers
calculated result to any memory location. SADR must have one memory location address to be calcu-
lated or immediate data and OADR must have the other memory location address to be calculated. Fixed
or relocatable address can be selected as source and destination addresses when using a memory +
memory calculation transfer. If the transfer source address is relocatable, the operation address also
becomes relocatable. Fixed or relocatable address can be selected as the transfer destination address
when using an immediate data + memory calculation transfer.
14.4 Transfer Modes
Single and burst transfers are available. The BRST bit in MOD selects transfer method, either single trans-
fer or burst transfer. COUNT determines how many transfers occur. No transfer occurs when COUNT is set
to "000016".
14.4.1 Single Transfer
For every transfer request source, DMAC II transfers one transfer unit of 8-bit or 16-bit data once. When
the source or destination address is relocatable, the address is incremented, after a transfer, for the next
transfer.
COUNT is decremented every time a transfer occurs. When using the end-of-transfer interrupt, the inter-
rupt is acknowledged when COUNT reaches "0".
14.4.2 Burst Transfer
For every transfer request source, DMAC II continuously transfers data the number of times determined
by COUNT. COUNT is decremented every time a transfer occurs. The burst transfer ends when COUNT
reaches "0". The end-of-transfer interrupt is acknowledged when the burst transfer ends if using the end-
of-transfer interrupt. All interrupts are ignored while the burst transfer is in progress.
14.5 Multiple Transfer
The MULT bit in MOD selects the multiple transfer. When using the multiple transfer, select the memory-to-
memory transfer. One transfer request source initiates multiple transfers. The CNT2 to CNT0 bits in MOD
selects the number of transfers from "0012" (once) to "1112" (7 times). Do not set the CNT2 to CNT0 bits to
"0002".
The transfer source and destination addresses for each transfer must be allocated alternately in addresses
following MOD and COUNT. When the multiple transfer is selected, the calculation transfer, burst transfer,
end-of-transfer interrupt and chained transfer cannot be used.
Rev. 1.03 Jul. 01, 2005 Page 149 of 494
REJ09B0037-0103