M32C85 Datasheet, PDF (200/542 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/85 Group (M32C/85, M32C/85T)
15. Timer (Timer B)
15.2.3 Pulse Period/Pulse Width Measurement Mode
In pulse period/pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal. (See Table 15.11) Figure 15.22 shows the TBiMR register (i=0 to 5) in pulse period/pulse
width measurement mode. Figure 15.23 shows an operation example in pulse period measurement
mode. Figure 15.24 shows an operation example in the pulse width measurement mode.
Table 15.11 Pulse Period/Pulse Width Measurement Mode Specifications
Item
Specification
Count Source
f1, f8, f2n(3), fC32
Counting Operation
• The timer increments a counter value
Counter value is transferred to the reload register on the valid edge of a pulse to be
measured. It is set to "000016" and the timer continues counting
Counter Start Condition
The TBiS bits (i=0 to 5) in the TABSR and TBSR register are set to "1" (starts counting)
Counter Stop Condition
The TBiS bit is set to "0" (stops counting)
Interrupt Request Generation Timing • On the valid edge of a pulse to be measured⁽¹⁾
• The timer counter overflows
The MR3 bit in the TBiMR register is set to "1" (overflow) simultaneously. When the
TBiS bit is set to "1" (start counting) and the next count source is counted after setting
the MR3 bit to "1" (overflow), the MR3 bit can be set to "0" (no overflow) by writing to
the TBiMR register.
TBiIN Pin Function
Read from Timer
Input for a pulse to be measured
The TBi register indicates reload register values (measurement results)⁽²⁾
Write to Timer
Value written to the TBi register can be written to neither reload register nor counter
NOTES:
1. No interrupt request is generated when the pulse to be measured is on the first valid edge after the
timer has started counting.
2. The TBi register is in an indeterminate state until the pulse to be measured is on the second valid
edge after the timer has started counting.
3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Rev. 1.03 Jul. 01, 2005 Page 177of 494
REJ09B0037-0103