M32C85 Datasheet, PDF (339/542 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/85 Group (M32C/85, M32C/85T)
22. Intelligent I/O (Communication Function)
Table 22.25 HDLC Processing Mode Specifications (Continued)
Item
Specification
Interrupt Request⁽¹⁾
During transmit data processing,
• One of the following conditions can be selected to set the GiTOR bit in the
interrupt request register to "1" (interrupt request) (see Figure 11.14).
_ _{When the IRS bit in the GiMR register is set to "0" (no data in the GiTB}
register) and data is transferred from the GiTB register to the transmit regis-
ter (transmit start).
_ _{When the IRS bit is set to "1" (transmission completed) and data transfer from}
the transmit register to the GiTO register is completed.
• When data, which is already converted to HDLC data, is transferred from the
receive register of the GiTO register to the transmit buffer, the GiTOR bit is set
to "1"
During received data processing,
• When data is transferred from the GiRI register to the GiRB register (reception
completed), the GiRIR bit is set to "1" (See Figure 11.14).
• When received data is transferred from the receive buffer of the GiRI register to
the receive register, the GiRIR bit is set to "1".
• When the GiTB register is compared to the GiCMPj register (j=0 to 3), the
SRTiR bit is set to "1".
NOTES:
1. See Figure 11.14 for details on the GiTOR bit, GiRIR bit and SRTiR bit.
Table 22.26 Clock Settings (Communication Unit 0)
Transfer Clock⁽¹⁾
CCS Register
CCS0 Bit
CCS1 Bit
f1
f8
f2n(2)
NOTES:
1
0
1
1
0
1
1. The transfer clock for reception is generated when the RSHTE bit in the G0ERC register is set to "1"
(receive shift operation enabled).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Table 22.27 Clock Settings (Communication Unit 1)
Transfer Clock⁽¹⁾
CCS Register
CCS2 Bit
CCS3 Bit
fBT1 (2)
0
0
2x(n+2)
f1
1
0
f8
1
1
f2n(3)
0
1
n: Setting value of the G1PO0 register, 000116 to FFFD16
NOTES:
1. The transfer clock for reception is generated when the RSHTE bit in the G1ERC register is set to "1"
(receive shift operation enabled).
2. The transfer clock is generated in single-phase waveform output mode of the channel 1.
3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Rev. 1.03 Jul. 01, 2005 ^{Page 316} of 494
REJ09B0037-0103