HN29V102414 Datasheet, PDF (43/48 Pages) Renesas Technology Corp – 1G AND type Flash Memory More than 32,113-sector (542,581,248-bit) x 2

HN29V102414 Series
Requirements for High System Reliability
The device may fail during a program, erase or read operation due to write or erase cycles. The following
architecture will enable high system reliability if a failure occurs.
1. For an error in read operation: An ECC (Error Correction Code) or a similar function which can correct
3-bits per each sectors is required for data reliability. When error occurs, data must not be corrected by
replacing to spare sector.
2. For errors in program or erase operations: The device may fail during a program or erase operation due to
write or erase cycles. The status register indicates if the erase and program operation complete in a finite
time. When an error occured in the sector, try to reprogram the data into another sector. Avoid further
system access to the sector that error happens. Typically, recommended number of a spare sectors are
1.8% (579 sectors/chip (min)) of initial usable 32,113 sectors/chip (min.) by each device. For the
reprogramming, do not use the data from the failed sectors, because the data from the failed sectors are not
fixed. So the reprogram data must be the data reloaded from the external buffer, or use the Data recovery
read mode or the Data recovery write mode (see the “Mode Description” and under figure “Spare Sector
Replacement Flow after Program Error”). To avoid consecutive sector failures, choose addresses of spare
sectors as far as possible from the failed sectors. In this case, 10⁵ cycles of program/erase endurance is
guaranteed.
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