M32C87 Datasheet, PDF (414/627 Pages) Renesas Technology Corp – MCU M16C FAMILY / M32C/80 SERIES

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 2 Communication Function)
22.5 Group 2 Communication Function
In the group 2 communication function, variable data length clock synchronous serial communication is available.
Figure 22.55 shows block diagram of group 2 communication function. Figures 22.56 to 22.60 show registers
associated with the communication function.
The signal output when G2POi register
(i = 0 to 7) matches a base timer
Channel 2
generation clock
ISCLK2
Clock
selecter
Bit
counter
G2TB register
Transmit shift
register
Transmit parity
calculation
Byte counter
ACK calculation
Receive parity
calculation
Output control
function
Latch
OPOL
Polarity
invert
Serial clock output from
ISCLK2 pin
Transfer data output from
ISTXD2 / IEOUT pin
Arbitration lost
detection
IEIN/
ISRXD2
Digital
filter
DF
0
1
IPOL
Polarity
invert
IE, serial
interface
interrupt control
Receive register
G2RB register
ID detection
All "F"
detection
Address detect
function
Statement
length detect
function
IE transmit interrupt request
(IE0R to IE2R)
IE receive interrupt request
(IE0R to IE2R)
Clock synchronous mode
transmit interrupt request
(SIO2TR)
Clock synchronous mode
receive interrupt request
(SIO2RR)
The signal output when G2PO6 or
G2PO7 register matches a base timer
Start bit detection
function
IE start bit interrupt request
(IE0R to IE2R)
OPOL, IPOL: Bits in the G2CR register
DF: Bit in the IECR register
IE0R to IE2R: Bits in registers IIO7IR and IIO8IR
SIO2TR : Bit in the IIO6IR register
SIO2RR: Bit in the IIO5IR register
NOTE:
1. After a clock, which is selected in the G2BCR0 register, is supplied to the registers, each register value becomes the after reset value.
Figure 22.55 Group 2 Communication Function Block Diagram
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 392 of 587