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M32C87 Datasheet, PDF (248/627 Pages) Renesas Technology Corp – MCU M16C FAMILY / M32C/80 SERIES
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
Table 17.3 Pin Settings in Clock Synchronous Mode
Port
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
P6_6
P6_7
P7_0(3)
P7_1
P7_2
P7_3
P9_0
P9_1
P9_2
P9_3
P9_4
P9_5
P9_6
P9_7
Function
PD6, PD7, PD9
Registers(2)
CTS0 input
PD6_0 = 0
RTS0 output −
CLK0 input
PD6_1 = 0
CLK0 output −
RXD0 input PD6_2 = 0
TXD0 output(4) −
CTS1 input
PD6_4 = 0
RTS1 output −
CLK1 input
PD6_5 = 0
CLK1 output −
RXD1 input PD6_6 = 0
TXD1 output(4) −
TXD2 output(4) −
RXD2 input PD7_1 = 0
CLK2 input
PD7_2 = 0
CLK2 output −
CTS2 input
PD7_3 = 0
RTS2 output −
CLK3 input
PD9_0 = 0
CLK3 output −
RXD3 input PD9_1 = 0
TXD3 output(4) −
CTS3 input
PD9_3 = 0
RTS3 output −
CTS4 input
PD9_4 = 0
RTS4 output −
CLK4 input
PD9_5 = 0
CLK4 output −
TXD4 output(4) −
RXD4 input PD9_7 = 0
Bit Setting
PSC, PSC3
Registers
PSL0, PSL1, PSL3
Registers
PS0, PS1, PS3
Registers(1)(2)
−
−
PS0_0 = 0
−
PSL0_0 = 0
PS0_0 = 1
−
−
PS0_1 = 0
−
PSL0_1 = 0
PS0_1 = 1
−
−
PS0_2 = 0
−
PSL0_3 = 0
PS0_3 = 1
−
−
PS0_4 = 0
−
PSL0_4 = 0
PS0_4 = 1
−
−
PS0_5 = 0
−
PSL0_5 = 0
PS0_5 = 1
−
−
PS0_6 = 0
−
PSL0_7 = 0
PS0_7 = 1
PSC_0 = 0
PSL1_0 = 0
PS1_0 = 1
−
−
PS1_1 = 0
−
−
PS1_2 = 0
PSC_2 = 0
PSL1_2 = 0
PS1_2 = 1
−
−
PS1_3 = 0
PSC_3 = 0
PSL1_3 = 0
PS1_3 = 1
−
−
PS3_0 = 0
−
PSL3_0 = 0
PS3_0 = 1
−
−
PS3_1 = 0
−
PSL3_2 = 0
PS3_2 = 1
−
PSL3_3 = 0
PS3_3 = 0
−
−
PS3_3 = 1
−
PSL3_4 = 0
PS3_4 = 0
−
−
PS3_4 = 1
−
PSL3_5 = 0
PS3_5 = 0
−
−
PS3_5 = 1
PSC3_6 = 0
−
PS3_6 = 1
−
−
PS3_7 = 0
NOTES:
1. Set registers PS0, PS1, and PS3 after setting the other registers.
2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do
not generate an interrupt or a DMA or DMACII transfer between these two instructions.
3. P7_0 is an N-channel open drain output port.
4. After UARTi (i = 0 to 4) operating mode is selected in the UiMR register and the pin function is set in the
Function Select Registers, the TXDi pin outputs an “H” signal until a transmit operation starts (the TXDi pin is in
a high-impedance state when N-channel open drain output is selected).
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 226 of 587
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