M32C87 Datasheet, PDF (110/627 Pages) Renesas Technology Corp – MCU M16C FAMILY / M32C/80 SERIES

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
9. Clock Generation Circuits
Count Source Prescaler Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCSPR
Address
035Fh
Bit Symbol
Bit Name
CNT0
Function
After Reset⁽²⁾
0XXX 0000b
RW
RW
CNT1
CNT2
Division rate select bits⁽¹⁾
If the setting value is n, f2n is the main clock,
RW
on-chip oscillator clock, or PLL clock divided
by 2n.
When n is set to 0, no division is selected
RW
CNT3
RW
−
(b6-b4)
Reserved bits
Read as undefined value
−
CST
Operation enable bit
0: Divider stops
1: Divider operates
RW
NOTES:
1. Set bits CNT3 to CNT0 after the CST bit is set to 0.
2. The TCSPR register maintains values set before reset, even after the software reset or watchdog timer reset has been performed.
Clock Prescaler Reset Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
0341h
After Reset
0XXX XXXXb
Bit Symbol
Bit Name
Function
RW
−
(b6-b0)
Unimplemented.
Write 0. Read as undefined value.
−
CPSR
Clock prescaler reset bit
When the CPSR bit is set to 1, a divider for
fC32 is reset. Read as 0.
RW
Figure 9.8 TCSPR Register, CPSRF Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
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